1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, to a three-dimensional chip packages.
2. Description of the Related Art
Computers and other electronic products use memory devices to store data and other information. In order to increase the amount of memory provided in a limited space, some memory devices have multiple semiconductor dice vertically arranged in a stack. Stacking memory chips is conventionally used to increase the capacity of a memory device while reducing I/O signaling power. One of the stacking approaches is System-in-Package (SiP), where a number of integrated circuits are enclosed in a single package or module. In the SiP, a number of integrated circuits are vertically stacked and are connected using conventional off-chip fine wires that are bonded to the package. Alternatively, with a flip-chip technology, solder bumps are used to join stacked chips together. This stacking approach allows higher density with reduced substrate footprint.
Recently, three-dimensional integrated circuits (3D IC) have been developed for improving the integration of the circuit components. 3D IC includes two or more layers of active electronic components integrated both vertically and horizontally into a single circuit. Unlike SiP, a 3D IC circuit may connect stacked semiconductor devices, such as memory devices, to a logic chip or other supporting substrate using vertical through-silicon vias (TSVs) running through the memory devices. TSV technology can be used for stacking a series of memory devices and provides a signal and/or heat path between the devices with shortened interconnect length and reduced power consumption by the memory devices.
One of the difficulties with TSV technology is the fairly limited memory capacity afforded by the memory devices stacked on logic chips. In cases where the logic chip is a graphics processing unit (GPU) chip 102 having a size of approximately 500 mm2 and the memory device is a planar dynamic random-access-memory (DRAM) chip 104 with an area of approximately 100-200 mm2 (as shown in FIGS. 1A and 1B), the size of the typical GPU chip 102 can only accommodate up to 4 stacks of 4 DRAM chip 104 (each DRAM chip 104 having a storage capacity of 256 Mbit) in order to create a total memory capacity of approximately 4 GBytes. The maximum frame buffer memory capacity is therefore limited to 4 GBytes due to limited size of the GPU chip.
Although TSV technology has been used to increase the data storage capacity of a memory device, the maximum memory capacity is still limited to a given size of the underlying logic chip supporting the memory devices. While a larger logic chip may increase the space for more stacked memory devices, the overall cost is increased accordingly.
As the foregoing illustrates, there is a need in the art for a cost-effective package system having a greater density of integrated circuits.